| |
LW1DSE > TECH 11.10.08 19:04l 148 Lines 7391 Bytes #999 (0) @ WW
BID : 630-LW1DSE
Read: GUEST
Subj: THE 8253 PART 1/2
Path: IZ3LSV<IK2XDE<F5GOV<F4DUR<CX2SA<CX4AE<LW1DRJ<LW8DJW
Sent: 081011/1629Z 3070@LW8DJW.#1824.BA.ARG.SA [Lanus Oeste] FBB7.00e $:630-LW1
From: LW1DSE@LW8DJW.#1824.BA.ARG.SA
To : TECH@WW
[――― TST HOST 1.43c, UTC diff:5, Local time: Sat Oct 11 10:50:09 2008 ®®®]
The 8253 Timer
Introduction:
The PC uses the Intel 8253 timer chip to perform various timing and
counting functions. The timer consists out of three counters called channels.
Each channel can be programmed to operate in 1 of 6 modes. Once programmed,
the channels can perform their tasks simultaneously. The timer is usually
assigned to IRQ-0 (highest priority hardware interrupt) because of the criti-
cal function it performs and because so many devices depend on it. There are
many uses for the timer within an operating or dedicated system:
Systems can use the timer to keep track of the current time of day.
Timers can be used to wait for a specific amount of time before continuing
with other operations. This is often necessary when programming complex
devices that require a certain amount of time to react to specific commands.
Operating systems such as Unix depend on the system clock and use it to
determine when a time slice for a process has expired so that another process
may be selected by the scheduler.
The 8253's Channels:
Each channel contains a 16-bit latch register and 16-bit counter.
Once the latch register is loaded, the value is transfered by the controller
to the counter register associated with the channel. Each channel is tied to
a 1.19318 MHz clock pulse. After every pulse, the counter associated with the
channel is decremented by one. Once the counter reaches zero, the channel
generates an interrupt signal on its output line. The way in which these
operations occur depends on the selected mode. The latch registers of the
timer channels (0,1 and 2) can be accessed through I/O ports 40H, 41H and 42H
respectively.
Most of the channels are allocated to predefined functions by the
BIOS during the initialization of the system at boot time. Channel 0 is
normally tied to IRQ-0 and usually controls the internal timing functions of
the BIOS through the handler installed at interrupt vector 08h (such as the
current time of day). Channel 1 is used to perform periodic DMA memory
refresh operations and should not be used for timing operations. Channel 2 is
tied to the PC's internal speaker and used to generate sound.
Programming the 8253:
Before any of the channels can be programmed, a command must be sent
to the timer through the command register at I/O port 43H. The format of the
command byte is as follows:
Command Register (Port 43H)
7 6 5 4 3 2 1 0
SC1 SC0 SL1 SL0 MODE BCD
SC1 and SC0 is used for channel selection. SC1 SC0 Result
0 0 Channel 0
0 1 Channel 1
1 0 Channel 2
SL1 and SL0 selects whether a store (write) or load (read) operation will be performed on the LSB, MSB or both the LSB and MSB of the counter register. Remember that the I/O port associated with the timer is only 8 bits wide, but the counter register is 16-bits wide. Two consecutive I/O instructions will be required to access both the LSB and MSB. SL1 SL0 Result
0 0 Latch present counter value
0 1 Read/Write MSB only
1 0 Read/Write LSB only
1 1 Read/Write LSB, then MSB
The MODE field selects the mode for the channel (000..101
Mode 0..Mode 5).
If BCD is set (BCD=1), then the counter will decrement in BCD rather than
binary.
Mode Selection
The 8253/8254 supports six different modes of operation that govern how and
when interrupts signals are generated.
Mode 0 - Countdown with optional inhibit (level output): This mode is used to
program single timeout operations. The output line of the timer is
automatically pulled low when this mode is selected. The counter
will decrement until terminal count is reached (counter register
becomes 0) and the output line is pulled high. The output line will
remain high until the counter is reloaded. However, the counter will
continue to decrement after terminal count is reached. The process
can be restarted by writing a new value into the latch registers or
by selecting a new mode. The first byte written to the controller
will inhibit the counting process and will only resume once the
second byte is written.
Mode 1 - Countdown with optional restart (level output): The output line will
be pulled low once the count register is loaded (triggered during
the rising edge of the gate input) and go low once terminal count is
reached. This mode is used to generate a single-shot interrupt with
a maximum duration of 54.9ms using an initial count value of 0.
Reloading the counter register will not affect the duration of the
output pulse until the succeeding trigger.
Mode 2 - Generate 1 pulse out of N: Once the latch register is loaded, its
contents is transferred to the counter register and the output line
is initially high. When the counter reaches one, the output line
goes low for one clock period (839ns). The count register is auto-
matically reloaded from the latch register and the process is
repeated. This mode allows the timer chip to generate a periodic
repeating signal.
Mode 3 - Generate square wave: This mode is exactly the same as mode 2,
except that the output line is high for exactly half the total count
and low for the other half. The result is a square wave signal on
the output line. The frequency of the wave is equal to the frequency
of the input clock signal divided by the counter value loaded into
the latch register.
Mode 4 - Countdown with optional inhibit (pulse output): This mode is similar
to mode 0, except that the output line is initially high and goes
low when terminal count is reached.
Mode 5 - Countdown with optional restart (pulse output): This mode is similar
to mode 1, except that the output line is initially high and goes
low when terminal count is reached.
Rate Selection
As mentioned earlier, the counter registers are tied to a clock
pulse generated at a frequency of 1.19318 MHz. The rate at which the timer
will generate interrupts can therefore be programmed by selecting a suitable
value and loading the counter through the latch register. For example, the
BIOS clock interrupt is generated 18.2 times every second. The reason for
this is that the BIOS loads the counter of channel 0 with a value of 0.
Loading the counter with a value of 0 sets the maximum number of decrement
operations (65536) before the counter reaches 0 again. Dividing the frequency
of the pulse by the counter register will yield an estimate on how many
interrupts will be generated per second:
1.19318 MHz * 1000000 = 1193180 Hz
1193180 / 65536 = 18.2
1/18.2 = 0.0549 seconds or roughly every 55ms
ΙΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝ»
Ί Osvaldo F. Zappacosta. Barrio Garay (GF05tg) Alte. Brown, Bs As, Argentina.Ί
Ί Mother UMC ζPC:AMD486@120MHz 32MbRAM HD SCSI 4.1Gb MSDOS 7.10 TSTHOST1.43C Ί
Ί Bater΅a 12V 70AH. 6 paneles solares 10W. Ί
Ί oszappa@yahoo.com ; oszappa@gmail.com Ί
ΘΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΝΌ
Read previous mail | Read next mail
| |
