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LW1DSE > TECH 29.05.11 16:27l 316 Lines 18139 Bytes #999 (0) @ WW
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Subj: How do MOSFET's work? (2/2)
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บ * Metal Oxide Semiconductors (MOS) * บ
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บ By LW1DSE บ
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( Best if viewed with CP 437 )
Part 2 of 2
4) MOSFET scaling
Over the past decades, the MOSFET has continually been scaled down in
size; typical MOSFET channel lengths were once several micrometres, but
modern integrated circuits are incorporating MOSFETs with channel lengths of
less than a tenth of a micrometre. Indeed Intel began production of a process
featuring a 65 nm feature size (with the channel being even shorter) in early
2006. Until the late 1990s, this size reduction resulted in great improvement
to MOSFET operation with no deleterious consequences. Historically, the
difficulties with decreasing the size of the MOSFET have been associated with
the semiconductor device fabrication process.
4.1) Reasons for MOSFET scaling
Smaller MOSFETs are desirable for several reasons. The main reason to
scale the transistors is to pack more and more devices in a given chip area.
This results in either smaller chips or chips with more computing power in
the same area. Since fabrication costs for a semiconductor wafer are
relatively fixed, the cost per integrated circuits is mainly related to the
number of chips that can be produced per wafer. Hence, smaller ICs allow more
chips per wafer, reducing the price per chip. In fact, over the past 30 years
the number of transistors per chip has been doubled every 2-3 years once a
new technology node is introduced. For example the number of MOSFETs in a
microprocessor fabricated in a 45 nm technology is twice as large as in a 65
nm chip. This doubling of the transistor count was first observed by Gordon
Moore in 1965 and is commonly referred to as Moore's law.
It is also expected that smaller transistors switch faster. While this
has been traditionally the case for the older technologies, for the
state-of-the-art MOSFETs scaling of the transistor dimensions doesn't
necessarily translate to higher speed. Commensurate scaling of the MOSFET
requires that all device dimensions are scaled with the same pace. The main
device dimensions are the transistor length, width, and the oxide thickness,
each (used to) scale with a factor of 0.7 per node. This way, the transistor
channel resistance doesn't change with scaling, while gate capacitance is cut
by a factor of 0.7. Hence, the RC delay of the transistor scales with a
factor of 0.7.
4.2) Difficulties arising due to MOSFET scaling
Producing MOSFETs with channel lengths much smaller than a micrometre
is a challenge, and the difficulties of semiconductor device fabrication are
always a limiting factor in advancing integrated circuit technology. In
recent years, the small size of the MOSFET, below a few tenths of a
micrometre, has created operational problems.
4.2.1) Subthreshold conduction
Because of small MOSFET geometries, the voltage that can be applied to
the gate must be reduced to maintain reliability. To maintain performance,
the threshold voltage of the MOSFET has to be reduced as well. As threshold
voltage is reduced, the transistor can't be completely turned off; that is,
the transistor operates in weak-inversion mode, with a subthreshold leakage,
or subthreshold conduction, between source and drain. Subthreshold conduction,
which was ignored in the past, now can consume upwards of half of the total
power consumption of modern high-performance VLSI chips.
Some micropower analog circuits are designed to take advantage of
subthreshold conduction; by working in the weak-inversion region, the MOSFETs
in these circuits deliver the highest possible transconductance-to-current
ratio.
4.2.2) Interconnect capacitance
Traditionally switching time was roughly proportional to the gate
capacitance of gates. However, with transistors becoming smaller and more
transistors being placed on the chip, interconnect capacitance (the
capacitance of the wires connecting different parts of the chip) is becoming
a large percentage of capacitance. Signals have to travel through the
interconnect, which leads to increased delay and lower performance.
4.2.3) Heat production
The ever-increasing density of MOSFETs on an integrated circuit is
creating problems of substantial localized heat generation that can impair
circuit operation. Circuits operate slower at high temperatures, and have
reduced reliability and shorter lifetimes. Heat sinks and other cooling
methods are now required for many integrated circuits including micro-
processors.
Power MOSFETs are at risk of thermal runaway. As their on-state
resistance rises with temperature, if the load is approximately a
constant-current load then the power loss rises correspondingly, generating
further heat. When the heatsink isn't able to keep the temperature low enough,
the junction temperature may rise quickly and uncontrollably, resulting in
destruction of the device.
4.2.4) Gate oxide leakage
The gate oxide, which serves as insulator between the gate and channel,
should be made as thin as possible to increase the channel conductivity and
performance when the transistor is on and to reduce subthreshold leakage when
the transistor is off. However, with current gate oxides with a thickness of
around 1.2 nm (which in silicon is ~5 atoms thick) the quantum mechanical
phenomenon of electron tunneling occurs between the gate and channel, leading
to increased power consumption.
Insulators (referred to as high-k dielectrics that have a larger
dielectric constant than silicon dioxide, such as group IVb metal silicates
e.g. hafnium and zirconium silicates and oxides are going to be used to
reduce the gate leakage from the 45 nanometer technology node onwards.
Increasing the dielectric constant of the gate oxide material allows a
thicker layer while maintaining a high capacitance. The higher thickness
reduces the tunneling current between the gate and the channel. An important
consideration is the barrier height of the new gate oxide; the difference in
conduction band energy between the semiconductor and the oxide (and the
corresponding difference in valence band energy) will also affect the leakage
current level. For the traditional gate oxide, silicon dioxide, the former
barrier is approximately 8 eV. For many alternative dielectrics the value is
significantly lower, somewhat negating the advantage of higher dielectric
constant.
4.2.5) Process variations
With MOSFETS becoming smaller, the number of atoms in the silicon that
produce many of the transistor's properties is becoming fewer. During chip
manufacturing, random process variation can affect the size of the transistor,
which becomes a greater percentage of the overall transistor size as the
transistor shrinks. The transistor characteristics become less deterministic,
but more statistical. This statistical variation increases design difficulty.
5) MOSFET construction
5.1) Gate material
The primary criterion for the gate material is that it is a good
conductor. Highly-doped polycrystalline silicon is an acceptable, but
certainly not ideal conductor, and it also suffers from some more technical
deficiencies in its role as the standard gate material. Nevertheless, there
are several reasons favoring use of polysilicon as a gate material:
* The threshold voltage (and consequently the drain to source on-current) is
modified by the work function difference between the gate material and
channel material. Because polysilicon is a semiconductor, its work function
can be modulated by adjusting the type and level of doping. Furthermore,
because polysilicon has the same bandgap as the underlying silicon channel,
it is quite straightforward to tune the work function, so as to achieve
low threshold voltages for both NMOS and PMOS devices. By contrast the work
functions of metals aren't easily modulated, so tuning the work function to
obtain low threshold voltages becomes a significant challenge. Additionally,
obtaining low threshold devices on both PMOS and NMOS devices would likely
require the use of different metals for each device type, adding additional
complexity to the fabrication process.
* The Silicon-SiO2 interface has been well studied and is known to have
relatively few defects. By contrast many metal-insulator interfaces contain
significant levels of defects which can lead to fermi-level pinning,
charging, or other phenomena that ultimately degrade device performance.
In the MOSFET IC fabrication process, it is preferable to deposit the
gate material prior to certain high-temperature steps in order to make better
performing transistors. Such high temperature steps would melt some metals,
limiting the types of metals that could be used in a metal-gate based process.
While polysilicon gates have been the defacto standard for the last twenty
years, they do have some disadvantages, which have led to the announcement of
their replacement by metal gates. These disadvantages include:
* Polysilicon is not a great conductor (approximately 1000 times more
resistive than metals) which reduces the signal propagation speed through
the material. The resistivity can be lowered by increasing the level of
doping, but even highly doped polysilicon isn't as conductive as most
metals. In order to improve conductivity further, sometimes a high
temperature metal such as tungsten, titanium, cobalt, and more recently
nickel, is alloyed with the top layers of the polysilicon. Such a blended
material is called silicide. The silicide-polysilicon combination has
better electrical properties than polysilicon alone and still doesn't melt
in subsequent processing. Also the threshold voltage isn't significantly
higher than polysilicon alone, because the silicide material isn't near the
channel. The process in which silicide is formed on both the gate electrode
and the source and drain regions is sometimes called salicide, self-aligned
silicide.
When the transistors are extremely scaled down, it is necessary to make
the gate dielectric layer very thin, around 1 nm in state-of-the-art
technologies. A phenomenon observed here is the so-called poly depletion,
where a depletion layer is formed in the gate polysilicon layer next to the
gate dielectric when the transistor is in the inversion. To avoid this
problem a metal gate is desired. A variety of metal gates such as tantalum,
tungsten, tantalum nitride, and titanium nitride are used, usually in
conjunction with high-k dielectrics. An alternative is to use fully-silicided
polysilicon gates, and the process is referred to as FUSI.
6) Other MOSFET types
6.1) Dual gate MOSFET
The dual gate MOSFET has a tetrode configuration, where both gates
control the current in the device. It is commonly used for small signal
devices in radio frequency applications where the second gate is normally
used for gain control or mixing and frequency conversion.
6.2) Depletion-mode MOSFETs
There are depletion-mode MOSFET devices, which are less commonly used
than the standard enhancement-mode devices already described. These are
MOSFET devices that are doped so that a channel exists even with zero voltage
from gate to source. In order to control the channel, a negative voltage is
applied to the gate (for an n-channel device), depleting the channel, which
reduces the current flow through the device. In essence, the depletion-mode
device is equivalent to a normally closed (on) switch, while the enhancement
mode device is equivalent to a normally open (off) switch (for example the
old 3N128).
Due to their low noise figure in the RF region, and better gain, these
devices are often preferred to bipolars in RF front-ends such as in TV sets.
Depletion-mode MOSFET families include BF 960 by Siemens and BF 980 by
Philips (dated 1980s), whose derivatives are still used in AGC and RF mixer
front-ends.
6.3) NMOS logic
n-channel MOSFETs are smaller than p-channel MOSFETs and producing only
one type of MOSFET on a silicon substrate is cheaper and technically simpler.
These were the driving principles in the design of NMOS logic which uses
n-channel MOSFETs exclusively. However, unlike CMOS logic, NMOS logic consumes
power even when no switching is taking place. With advances in technology,
CMOS logic displaced NMOS logic in the 1980s to become the preferred process
for digital chips.
6.4) Power MOSFET
Power MOSFETs have a different structure than the one presented above.
As with all power devices, the structure is vertical and not planar. Using a
vertical structure, it is possible for the transistor to sustain both high
blocking voltage and high current. The voltage rating of the transistor is a
function of the doping and thickness of the N epitaxial layer (see cross
section), while the current rating is a function of the channel width (the
wider the channel, the higher the current). In a planar structure, the current
and breakdown voltage ratings are both a function of the channel dimensions
(respectively width and length of the channel), resulting in inefficient use
of the "silicon estate". With the vertical structure, the component area is
roughly proportional to the current it can sustain, and the component
thickness (actually the N-epitaxial layer thickness) is proportional to the
breakdown voltage (for example, IRF840 and STP6N60).
It is worth noting that power MOSFETs with lateral structure are mainly
used in high-end audio amplifiers. Their advantage is a better behaviour in
the saturated region (corresponding to the linear region of a bipolar
transistor) than the vertical MOSFETs. Vertical MOSFETs are designed for
switching applications.
6.5) DMOS
DMOS stands for double-Diffused Metal Oxide Semiconductor. Most of the
power MOSFETs are made using this technology.
7) MOSFET analog switch
MOSFET analog switches use the MOSFET channel as a low-on-resistance
switch to pass analog signals when on, and as a high impedance when off.
Signals flow in both directions across a MOSFET switch. In this application
the drain and source of a MOSFET exchange places depending on the voltages of
each electrode compared to that of the gate. For a simple MOSFET without an
integrated diode, the source is the more negative side for an N-MOS or the
more positive side for a P-MOS. All of these switches are limited on what
signals they can pass or stop by their gate-source, gate-drain and
source-drain voltages, and source-to-drain currents; exceeding the voltage
limits will potentially damage the switch.
7.1) Single-type MOSFET switch
This analog switch uses a four-terminal simple MOSFET of either P or N
type. In the case of an N-type switch, the body is connected to the most
negative supply (usually GND) and the gate is used as the switch control.
Whenever the gate voltage exceeds the source voltage by at least a threshold voltage, the MOSFET conducts. The higher the voltage, the more the MOSFET can conduct. An N-MOS switch passes all voltages less than (Vgate-Vtn). When the switch is conducting, it typically operates in the saturation region, since the source and drain voltages will typically be nearly equal.
In the case of a P-MOS, the body is connected to the most positive voltage,
and the gate is brought to a lower potential to turn the switch on. The P-MOS
switch passes all voltages higher than (Vgate+Vtp). Threshold voltage (Vtp)
is typically negative in the case of P-MOS.
A P-MOS switch will have about three times the resistance of an N-MOS
device of equal dimensions because electrons have three times the mobility of
holes in silicon.
7.2) Dual-type (CMOS) MOSFET switch
This "complementary" or CMOS type of switch uses one P-MOS and one
N-MOS FET to counteract the limitations of the single-type switch. The FETs
have their drains and sources connected in parallel, the body of the P-MOS is
connected to the high potential (VDD) and the body of the N-MOS is connected
to the low potential (Gnd). To turn the switch on the gate of the P-MOS is
driven to the low potential and the gate of the N-MOS is driven to the high
potential. For voltages between (VDD-Vtn) and (Gnd+Vtp) both FETs conduct the
signal, for voltages less than (Gnd+Vtp) the N-MOS conducts alone and for
voltages greater than (VDD-Vtn) the P-MOS conducts alone.
The only limits for this switch are the gate-source, gate-drain and
source-drain voltage limits for both FETs. Also, the P-MOS is typically three
times the width of the N-MOS so the switch will be balanced. Tri-state
circuitry sometimes incorporates a CMOS MOSFET switch on its output to
provide for a low ohmic, full range output when on and a high ohmic, mid
level signal when off.
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