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LW1DSE > TECH 21.08.10 21:24l 258 Lines 13201 Bytes #999 (0) @ WW
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Subj: Understanding FET's
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ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»
º * JFET's * º
ÈÍÍÍÍÍÍÍÍÍÍÍÍÍͼ
To be viewed in ASCII CP437
The junction gate field-effect transistor (JFET or JUGFET) is the
simplest type of field effect transistor. Like other transistors, it can be
used as an electronically-controlled switch. It is also used as a
voltage-controlled resistance. An electric current flows from one connection,
called the source, to a second connection, called the drain. A third
connection, the gate, determines how much current flows. By applying an
increasing negative (for an n-channel JFET) bias voltage to the gate, the
current flow from source to drain can be impeded by pinching off the channel,
in effect switching off the transistor.
Contents:
1) Structure
2) Function
3) Schematic symbols
4) Comparison with other transistors
5) Uses nd examples
1) Structure
o Drain
³
ÚÄÄÄÂÄÄÁÄÄÂÄÄÄ¿ Fig 1: An internal view
³ ÀÄÄÄÄÄÙ ³ of an imaginary
³ ³ Jfet
³ ³
±±±±±±±±±±±±±±±ÄÄo Gate
³ ³
³ ³
³ ÚÄÄÄÄÄ¿ ³
ÀÄÄÄÁÄÄÂÄÄÁÄÄÄÙ
³
o Source
The JFET consists of a long channel of semiconductor material. This
material is doped so that it contains an abundance of positive charge
carriers (p-type), or of negative charge carriers (n-type). There is a
contact at each end; these are the source and drain. The third control
terminal, the gate, surrounds the channel, and is doped opposite to the
doping-type of the channel, forming a p-n junction at the interface of the
two types of the material. Terminals to connect with the outside are usually
made Ohmic.
2)Function
The operation of a JFET is analogous to a garden hose. The flow of
water through a garden hose can be controlled by squeezing it and reducing
its cross section; the flow of electric charge through a JFET is controlled
by constricting the cross section of the current-carrying channel.
3) Schematic symbols
Sometimes the JFET gate is drawn in the middle of the channel instead
of at the drain/source electrode as in these examples. This symmetric
variation is hinting that the channel is indeed symmetric in the sense that
drain and source are interchangeable physical terminals. So this symbol
variation should be used only for JFETs where drain and source indeed are
interchangeable, which isn't true for all JFETs.
Drain D
³ ³
ÇÄÄÙ N channel ÇÄÄÙ P channel
º º
Gate ÄÄ>ÇÄÄ¿ G ÄÄ<ÇÄÄ¿
³ ³
Source S
Fig. 2: JFET N & P channel schematics.
D D
³ ³
ÇÄÄÙ N channel ÇÄÄÙ P channel
ÄÄ>º G ÄÄ<º
Gate ÇÄÄ¿ ÇÄÄ¿
³ ³
S S
Fig 3: alternate schematic drawings
Traditionally, the US style of the symbol was drawn with the whole
component inside a circle, although this has been simplified in favor of the
European style to draw it without a circle.
In every case the arrow head indicates the polarity of the P-N-junction
of the gate in relationship to the channel. (As in a diode, the arrow points
from P to N, indicating the direction of current flow when forward-biased. A
mnemonic for remembering the N-channel device is that the arrow "points iN".)
In order to pinch off the channel, one must produce a certain voltage
in reverse direction (VGS) of that junction. The precise value of this pinch
off voltage varies with individual JFETs, even with JFETs of the same type,
typical values ranging between 0.5 to 10 V.
The appropriate voltage bias can be remembered easily, since the
n-channel device requires a negative gate-source voltage (VGS) to switch off
the JFET, while the p-channel device requires a positive gate-source voltage
(VGS) to switch off the JFET.
Examples of such devices are: MPF102 (Motorola), BF245 (Philips),
2N3819 (Texas Instruments)(singles) and 2N3858 dual JFET from National
Semiconductor. In the japanese nomenclature, 2SKxxx means a NJFET and 2SJxxx
a P device; 2SK19 from Toshiba. US manufactures don't distinguishes the
channel polarity in the part number.
4)Comparison with other transistors:
The JFET gate presents a small current load which is the reverse
leakage of the gate-to-channel junction. The MOSFET has the advantage of
extremely low gate current (measured in picoamperes) because of the
insulating oxide between the gate and channel. However, compared to the base
current of a bipolar junction transistor the JFET gate current is much lower,
and the JFET has higher transconductance than the MOSFET. Therefore JFETs are
used to advantage in some low-noise, high input-impedance op-amps (i.e.: ST's
series of operational amps: TL081 single, TL082 dual and TL084 quad) and
sometimes used in switching applications.
The JFET had been predicted as early as 1925 by Julius Lilienfeld, and
the theory of operation of the device was sufficiently well known by the mid
30's for a patent to be issued for it. However, technology at the time wasn't
sufficiently advanced to produce doped crystals with enough precision for the
effect to be seen until many years later. In 1947, researchers John Bardeen,
Walter Houser Brattain, and William Shockley were attempting to construct a
JFET when they discovered the bipolar junction transistor when the gate fused.
The first practical JFETs were thus constructed many years after the first
when junction transistors, in spite of having been invented much earlier.
5) Uses and examples:
A common-source (often abbreviated to CS) amplifier is one of the three
possible amplifier circuit configurations that use a single field effect
transistor (FET) as the active device. The name derives from the fact that
the FET's source terminal is connected to neither the input nor the output
path and hence is 'common'.
The CS amplifier is conceptually a voltage amplifier. The input voltage
modulates the amount of current flowing through the FET, changing the voltage
across the output resistance according to Ohm's law. Alternatively, the CS
amplifier can be treated as a transconductance amplifier, with the input
voltage modulating the current going to the load. However, the FET device's
output resistance isn't typically low enough for a decent voltage amplifier,
or high enough for a reasonable transconductance amplifier. Another major
drawback is the amplifier's limited high-frequency response. Therefore, in
practice the output is routed through a common drain (CD) or common gate (CG)
stage, which have more favorable output and frequency characteristics. Hybrid
circuit arrangements are possible; an example is the cascode, which (in its
FET incarnation) is a consolidated CS-CG amplifier.
ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ¿
³ ³
± Rd 10Kê ³ +
± ÄÄÁÄÄ
³ Cd 1 æF ÜÜÜ VDD
ÃÄÄÄÄÄÄÄÄÄÄ´ÃÄÄÄÄ¿ ³
³ ³ ³ 12V
Cg .1 æF ÇÄÄÙ ³ ³
oÄÄÄ´ÃÄÄÄÂÄÄÄ>º + - ³ ³
³ ÇÄÄÂÄÄ´ÃÄ¿ 100æF o ³
Rg ± ³ ³ ³ Fig 4: Example of
IN ± ± Rs ³ Out ³ common source
1Mê ³ ± 1Kê ³ ³ amplifier.
³ ³ ³ o ³
oÄÄÄÄÄÄÄÄÁÄÄÄÄÄÄÄÁÄÄÄÄÄÁÄÄÄÄÄÄÄÄÄÄÁÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ´
Á GND (common)
ÚÄÄÄÄÄÄÄÄÄÄÄÂÄÄÄÄÄÄÄÄÄÄÄo + Vdd
³ ³
± ± Rd
± R1 ±
³ ³ Cd
³ ÃÄÄÄÄÄÄÄÄÄÄ´ÃÄÄÄÄo
Cbp ³ Vdd/2 ÇÄÄÙ J2 OutPut
ÚÄÄ´ÃÄÄÄÅÄÄÄÄÄÄÄ>º N Type (Common gate amplifier)
Á ³ ÇÄÄ¿
GND ± ³
± R1 ³
³ ³
Á GND ³
Cg ÇÄÄÙ J1 N Type (Common source amplifier)
oÄÄÄ´ÃÄÄÄÂÄÄÄ>º
³ ÇÄÄÂÄÄ´ÃÄ¿
Rg ± ³ ³ Fig 5: Example of
InPut ± ± Rs ³ JFET cascode
³ ± 1Kê ³ amplifier.
³ ³ ³
oÄÄÄÄÄÄÄÄÁÄÄÄÄÄÄÄÅÄÄÄÄÄÁÄÄ Cbp: By Pass at working frequency
Á GND
Cbp
ÚÄÄÄ´ÃÄÄÄÂÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÂÄÄÄÄÄÄÄÄÄo + Vdd
GND Á ³ ³
³ $ RFC
ÇÄÄÙJ1 $
ÚÄÄÄÄÂÄÄÄÄÂÄÄÄÄÄ>º $ Cbp Out
³ ³ ³ ÇÄÄ¿ ÃÄÄÄÄÄ´ÃÄÄo
³ Rg ± ³C1 ³ C3 ³ Fig 6: Example of
³ ± Ø ³ ÇÄÄÙ JFET Xtal Oscillator
Á ³ ÃÄÄÄÄÄÄÄÄÄÅÄ´ÃÄÄÄÂÄÄÄÄ>º J2 and buffer stage.
²²² ³ Ø $ ± ÇÄÄ¿
 ³ ³C2 $ RFC ± Rg ³ Note: Xtal may be
³ ³ ³ $ ³ ³ replaced by a series
ÀÄÄÄÄÁÄÄÄÄÅÄÄÄÄÄÄÄÄÄÁÄÄÄÄÄÄÁÄÄÄÄÄÄÄÄÁÄÄÄÄÄÄÄÄÄo resonant tank circuit
Xtal Á GND to make a JFET Clapp
oscillator circuit.
RFC: Choque coil (high Xl at working frequency)
Cbp: By Pass at working frequency
ÚÄÄÄÄÄÄÄÄÄÄÄÂÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄo +Vdd
Rd1 ± ± Rd2
± ±
³ ³
ÃÄÄÄÄÄÄÄÄÄÄÄ)ÄÄÄÄÄÄÄÄÄo Vo1
ÇÄÄÙ ³
oÄÄÄÄÄÄÄÂÄÄÄÄÄÄÄÄÄ>º J1 ³
Vi1 ± ÇÄÄ¿ ³
± Rg1 ³ ÃÄÄÄÄÄÄÄÄÄo Vo2
Á ³ ³
³ ³
³ ÇÄÄÙ
oÄÄÄÄÄÄÄÂÄÄÄÄÄÄÄÄÄÄÄÄÄ)ÄÄÄÄÄÄÄ>º J2
Vi2 ± ³ ÇÄÄ¿ Fig 7: JFET differetial
± Rg2 ³ ³ amplifier with JFET
Á ÃÄÄÄÄÄÄÄÄÄÄÄÙ current source at the
³ common sourcesjunction.
ÇÄÄÙ
ÚÄÄ>º J2
³ ÇÄÄ¿ (Vo1-Vo2)= - Av (Vi1-Vi2)
³ ³ Av: Voltage gain
³ ± Rs3 - indicates polarity inversion
³ ± at output with respect to
³ ³ the input.
ÀÄÄÄÄÄÄÁÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄo -Vss
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º Compilled from Wikipedia.com . Translatted and ASCII schematics by LW1DSE º
º Osvaldo F. Zappacosta. Barrio Garay, Almirante Brown, Bs As, Argentina. º
º Made with MSDOS 7.10's Text Editor (edit.com) in my AMD's 80486. º
º August 20, 2010 º
ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ
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º Osvaldo F. Zappacosta. Barrio Garay (GF05tg) Alte. Brown, Bs As, Argentina.º
º Mother UMC æPC:AMD486@120MHz, 16MbRAM HD IDE 1.6Gb MSDOS 7.10 TSTHOST1.43C º
º Bater¡a 12V 160AH. 9 paneles solares 10W. º
º oszappa@yahoo.com ; oszappa@gmail.com º
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