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G8MNY > TECH 16.05.25 10:00l 54 Lines 2159 Bytes #999 (0) @ WW
BID : 32674_GB7CIP
Read: GUEST
Subj: Mono Stable Revisited
Path: IZ3LSV<IW0QNL<JH4XSY<JE7YGF<LU4ECL<VK2RZ<IR0AAB<I0OJJ<I0OJJ<GB7CIP
Sent: 250516/0745Z @:GB7CIP.#32.GBR.EURO #:32674 [Caterham Surrey GBR]
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From: G8MNY@GB7CIP.#32.GBR.EURO
To : TECH@WW
By G8MNY (Updated Sep 18)
(8 Bit ASCII graphics use code page 437 or 850, Terminal Font)
I needed a timer to timeout a 0V ON signal, on a Tx after a few minutes for RDS
Trafic flag. I had done it before with a 555 timer & input & output
conditioning inverters, all far too complex really. So I had a re-think on the
basic 2 transistor circuit, & came up with this simple junk box design.
A simular circuit can be used on PTT line of most Tx to limit key up time!
+5-20V >ÄÄÂÄÄÄÄÂÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÂÄÄÄÄÄÄÄ¿
10K ³ 33K 1K
³ 2M2 ³ _³_
³ ³R ³ LED=\_/ Time
³ ³ BC337ÃÄ¿ ÃÄÄÄÄÄÄ>Limited
Low ³ + ³ T1³/ ³ ³/BC337 Low Output
Input >ÄÄÄÁÄ´ÃÄÁÄ10KÄÂÄÄ´>ÃÄÄ´ ÀÄÄÄ´ T2
C 100u === * ³\e ³\e
u1 ³ ³ ³
0V >ÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÁÄÄÄÄÄÄÄÄÄÁÄÄÄÄÄÄÄÁÄÄÄÄÄÄ>
With no input, T1 is on & T2 held off. The 33K must be low enough to get 0V out
of T2 with required load, & the 2M2 must be low enough for T1 to turn off T2.
Higher gain transistor like the BC109c (Beta = 900) can be used for T1 with R
of 10M for longer times, if the cap C is realy low leakage.
With the input low, a negative voltage equal to the power rail, is appled to
T1's base & diode, holding it off for around 200 seconds. The CR time constant
of 2M2 with the 100uF cap sets the time, but a leaky C will only shorten the
time slighty in this circuit.
T1s Base 10K & u1 give basic false pulse/RF imunity.
On 5V the diode (* 1N4148) can be omitted as it is not needed to protect T1's
base from going too negative & damaging T1.
Why Don't U send an interesting bul?
73 De John, G8MNY @ GB7CIP
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